This invention is directed to a method for fabricating chips having embedded memory and other components, such as logic circuits. More particularly, this invention is directed to a simple method for providing plugs and local interconnects in chips having embedded DRAM.
Combining both embedded DRAM memory and other components, such as high speed logic circuits, onto a single chip is often useful. For example, U.S. Pat. No. 5,883,814 discloses advantages to such a system-on-chip (SOC) including faster speed and overcoming bandwidth and capacitance problems associated with off-chip connections between arrays of memory and logic.
Systems-on-chip include memory-in-logic, where memory circuits are embedded in primarily logic blocks and logic-in-memory which are predominantly memory blocks with some logic circuitry. Increasingly important applications for systems-on-chip include high-performance, low-power multi-media apparatus.
In systems comprising both memory and logic, both the memory and logic are preferably made with as many common processing steps as possible. However, many process steps that are conveniently used for logic and SRAM applications, such as metal local interconnects, are not practical for embedded memory applications, specifically DRAM, because of the leakage/refresh requirements for the DRAM process.
A hallmark of this invention is a process for fabricating low resistance local interconnects and polysilicon plugs for a combined embedded memory/logic array.
The applicants have found via this invention that the formation of low resistance interconnects and plugs with metal silicide interconnects can be used in the same chip with DRAM arrays.
One embodiment of the invention is a method of fabricating silicided plugs, the method comprising the steps of: (i) providing a silicon substrate having at least one N-type doped region and at least one P-type doped region, wherein the N-type doped region and P-type doped region are arranged to form at least one diffused source/drain junction or are separated by isolation wherein the silicon substrate is overlaid with an insulative layer; (ii) opening a first bole in the insulative layer to expose the diffused source/drain junction (if present) and at least part of the N-type doped region or P-type doped region; (iii) forming a layer of a first highly doped polysilicon having the same doping as the region exposed in step (ii) within the first hole to form a first plug, such that the layer of first highly doped polysilicon is at least as high as the insulative layer; (iv) opening a second hole in the insulative layer adjacent to the first plug to expose at least part of the doped region having a different type doping than the first highly doped polysilicon; (v) forming a layer of a second highly doped polysilicon, having the same type doping as the region exposed by the second hole, within the second hole to form a second plug abutting the first plug, such that the layer of second highly doped polysilicon is at least as high as the insulative layer; and, (vi) forming a metal silicide layer on top of both the first plug and the second plug electrically connecting the first and second plugs (local interconnect).
Another preferred embodiment of the invention is a method of fabricating a system-on-chip, the method comprising the steps of: (i) providing a semiconductor device comprising a silicon substrate, the silicon substrate having arrayed thereon at least one first component comprising a DRAM wordline and at least one second component selected from the group consisting of a device comprising a logic gate, an SRAM or a combination thereof, wherein the silicon substrate, the first component and the second component are overlaid with a layer of an insulative material, wherein a first silicon plug, in electrical contact with the first component and second component, extends through the layer of insulative material to the silicon substrate of like doping and a second silicon plug, in electrical contact with the second component, extends through the layer of protective material to the silicon substrate of like doping; and (ii) forming a metal silicide layer on the first plug and the second plug creating a local interconnect in the second component.
Another preferred embodiment of the invention is a method of fabricating a system-on-chip, the method comprising the steps of: (i) providing a semiconductor device comprising a silicon substrate, the silicon substrate having arrayed thereon at least one first component comprising a DRAM wordline and at least one second component selected from the group consisting of a device comprising a logic gate, an SRAM or a combination thereof, wherein the silicon substrate, the first component and the second component are overlaid with a layer of a insulative material, wherein a first silicon plug, in electrical contact with the first component and second component, extends through the layer of insulative material to the silicon substrate of like doping and a second silicon plug, in electrical contact with the second component, extends through the layer of insulative material to the silicon substrate of like doping; (ii) depositing a second insulative layer on top of the first insulative material, the first plug and the second plug; (iii) opening a hole in the second insulative layer to expose a local interconnect pattern for the second component; and (iv) depositing a layer of refractory metal (and associated thin barrier/adhesive layers of Titanium (Ti)/Titanium nitride (TiN)) in the hole to form a local interconnect.
Still another preferred embodiment of the invention is a method of fabricating a system-on-chip, the method comprising the steps of: (i) providing a semiconductor device comprising a silicon substrate, the silicon substrate having arrayed thereon at least one first component comprising a DRAM wordline and at least one second component selected from the group consisting of a device comprising a logic gate, an SRAM or a combination thereof, wherein the silicon substrate, the first component and the second component are overlaid with a layer of a insulative material, wherein a first silicon plug, in electrical contact with the first component and second component, extends through the layer of protective material to the silicon substrate of like doping and a second silicon plug, in electrical contact with the second component, extends through the layer of insulative material to the silicon substrate of like doping; (ii) depositing a second insulative layer on top of the layer of first insulator material, the first plug and the second plug; (iii) opening a first hole in the second insulator layer to expose a local interconnect pattern for the second component; (iv) opening a second hole in the second insulator layer to expose the top of the first plug; and (v) depositing a layer of refractory metal (and associated thin barrier/adhesive layers of Ti/TiN) in the first hole to form a first local interconnect and in the second hole to form a bottom electrode.
Another embodiment of the invention is a system-on-chip comprising: (i) a silicon substrate, the silicon substrate having arrayed thereon at least one first component comprising a DRAM wordline and at least one second component selected from the group consisting of a device comprising a logic gate, an SRAM or a combination thereof; (ii) a layer of a insulative material overlaying the silicon substrate, the first component and the second component, wherein a first silicon plug, in electrical contact with the first and second component, extends through the layer of protective material to the silicon substrate of like doping and a second silicon plug, in electrical contact with the second component and abutting first plug, extends through the layer of insulative material to the silicon substrate of like doping; and (iii) a local interconnect comprising a salicide layer located over, and in electrical contact with, the first silicon plug and the second silicon plug.